In the filed of flat display, liquid crystal display devices have been widely applied in end display apparatuses of various sizes due to their characteristics such as light weight, small volume and thin thickness, etc. The display panel of a traditional liquid crystal display device is constituted by an array substrate and a liquid crystal layer sandwiched between opposite substrates, and on the array substrate is arranged a vertical and horizontal array type pixel matrix, wherein the pixel structure of the array substrate comprises a thin film transistor (TFT) and a pixel electrode, and the pixel electrode and the common electrode constitute a capacitor, and the TFT inputs a different voltage to the pixel electrode under the control of crossed data lines and scanning lines, a different electric field is therefore formed on the liquid crystal capacitor, and the electric field controls the liquid crystal deflection and accomplishes the display function of the panel.
With the development of technology, there appears a gate driver on array (GOA) technique. The GOA technique is one that integrates a scanning circuit onto an array substrate, and as a shift register, each GOA unit successively passes a scanning signal to a next GOA unit to turn on TFT switches line by line and accomplish data signal input of pixel units. A gate driving circuit of the GOA technique comprises a plurality of signal lines for providing a signal(s) and a shift register for storing signal data. As shown in FIG. 1, for ease of illustration, a signal line is marked with a signal which is transferred by the signal line as follows.
The signal lines comprise a trigger signal line for inputting an initial trigger signal STV to a shift register, a pull-low signal line for inputting a low level signal VSS to a shift register, a first clock signal line and a second clock signal line for providing a shift register with complementary clock pulse signals, namely, a first clock signal CLK and a second clock signal CLKB.
The shift register comprises a pull-up driving unit, a pull-up unit, a pull-down driving unit, a pull-down unit and a reset unit.
The pull-up driving unit is connected to the trigger signal line for transferring the trigger signal STV, to the second clock signal line for transferring the second clock signal CLKB, and to a pull-up node PU, the pull-up unit is connected to the first clock signal line for transferring the first clock signal CLK, the pull-up node and an output signal terminal, the pull-down driving unit is connected to the second clock signal line, the pull-up node PU, a pull-down node PD and a low level signal terminal VSS, the pull-down unit is connected to the second clock signal line, the pull-up node PU, the pull-down node PD, the low level signal terminal VSS and the output signal terminal, and the reset unit is connected to the pull-up node PU, the pull-down node PD, the low level signal terminal VSS and a reset signal line for transferring a reset signal.
However, when the gate driving circuit comprising a shift register as described above scans, it is necessary to change the direction of the electric field on the liquid crystal capacitor (i.e., polarity reversal) for each frame, and during the polarity reversal, due to the leakage of the TFT and the crosstalk of the parasitic capacitance, it will result in that the positive and negative charges on both electrodes of the liquid crystal capacitor may not be completely offset, and residual DC charges are accumulated on the electrodes, which affect the liquid crystal deflection and thereby form a residual image.